// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See VRISCV_BOARD.h for the primary calling header

#ifndef VERILATED_VRISCV_BOARD___024ROOT_H_
#define VERILATED_VRISCV_BOARD___024ROOT_H_  // guard

#include "verilated.h"

class VRISCV_BOARD__Syms;
class VRISCV_BOARD___024unit;


class VRISCV_BOARD___024root final : public VerilatedModule {
  public:
    // CELLS
    VRISCV_BOARD___024unit* __PVT____024unit;

    // DESIGN SPECIFIC STATE
    // Anonymous structures to workaround compiler member-count bugs
    struct {
        VL_IN8(clk,0,0);
        VL_IN8(reset,0,0);
        VL_OUT8(debug_wb_rf_wen,0,0);
        VL_OUT8(debug_wb_rf_waddr,4,0);
        CData/*0:0*/ RISCV_BOARD__DOT__inst_sram_en;
        CData/*3:0*/ RISCV_BOARD__DOT__data_sram_wmask;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_allowin;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_allowin;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2;
        CData/*2:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak;
        CData/*7:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0;
        CData/*4:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__mem_valid;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0;
        CData/*0:0*/ RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid;
        CData/*4:0*/ __VdfgTmp_hea37eb48__0;
        CData/*4:0*/ __Vtrigrprev__TOP__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel;
        CData/*0:0*/ __VstlDidInit;
        CData/*0:0*/ __Vtrigrprev__TOP__clk;
        CData/*0:0*/ __VactDidInit;
        CData/*0:0*/ __VactContinue;
        SData/*10:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__alu_op;
        SData/*8:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37;
        VL_OUT(debug_wb_pc,31,0);
        VL_OUT(debug_wb_rf_wdata,31,0);
        IData/*31:0*/ RISCV_BOARD__DOT__inst_sram_addr;
        IData/*31:0*/ RISCV_BOARD__DOT__inst_sram_rdata;
        IData/*31:0*/ RISCV_BOARD__DOT__data_sram_rdata;
        VlWide<7>/*212:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus;
    };
    struct {
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc;
        VlWide<3>/*95:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec;
        VlWide<10>/*315:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b;
        IData/*31:0*/ RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result;
        VlWide<7>/*217:0*/ RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r;
        VlWide<7>/*212:0*/ RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r;
        IData/*31:0*/ __VstlIterCount;
        IData/*31:0*/ __VicoIterCount;
        IData/*31:0*/ __VactIterCount;
        VlUnpacked<IData/*31:0*/, 32> RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf;
    };
    VlTriggerVec<2> __VstlTriggered;
    VlTriggerVec<1> __VicoTriggered;
    VlTriggerVec<2> __VactTriggered;
    VlTriggerVec<2> __VnbaTriggered;

    // INTERNAL VARIABLES
    VRISCV_BOARD__Syms* const vlSymsp;

    // CONSTRUCTORS
    VRISCV_BOARD___024root(VRISCV_BOARD__Syms* symsp, const char* v__name);
    ~VRISCV_BOARD___024root();
    VL_UNCOPYABLE(VRISCV_BOARD___024root);

    // INTERNAL METHODS
    void __Vconfigure(bool first);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);


#endif  // guard
